• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A power up detector is provided to generate a power up signal stably even when a voltage level is unstable or there is noise. CONSTITUTION: A voltage divider unit(10) divides an input power supply voltage with a constant ratio. A potential detection unit compares the divided potential with a specific potential, and then outputs its comparison result. A buffer unit changes a level of the comparison result when the comparison result being output from the potential detection unit maintains a constant potential.
    公开号:KR20040061853A
    申请号:KR1020020088153
    申请日:2002-12-31
    公开日:2004-07-07
    发明作者:강창석；이재진
    申请人:주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    [0001] Apparatus for detecting power up [0002]
    [6] BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a power-up detection device for detecting a time point when a power source voltage becomes a predetermined voltage or higher, and more particularly, to a power-up detection device performing stable operation without being affected by power noise.
    [7] In general, the power-up detection device detects a power supply voltage applied from the outside to initialize the semiconductor device before the power supply voltage becomes higher than a specific potential, and causes the semiconductor device to operate when the power supply voltage is higher than a specific potential.
    [8] 1 is a circuit diagram showing a conventional power-up detection apparatus.
    [9] The power-up detection apparatus includes a voltage divider (1) for distributing a power supply voltage VCC at a predetermined ratio, a resistor (R1) having one terminal connected to the power supply voltage (VCC), and a ground terminal An inverter INV1 for inverting the potential N1 of the common node between the resistor R1 and the NMOS transistor NM1 and a signal N2 output from the inverter INV1 And a buffer 2 for buffering and outputting the power-up detection signal PWR.
    [10] Here, the voltage divider 1 includes two resistors R2 and R3 connected in series between the power supply voltage VCC and the ground voltage, and outputs the potential N0 distributed from the common node of the two resistors R2 and R3.
    [11] The buffer 2 includes two inverters INV2 and INV3 for sequentially inverting the signal N2 output from the inverter INV1.
    [12] The operation of the power-up detecting apparatus according to the related art will now be described.
    [13] The power-up detection device detects the potential of the external power supply voltage VCC when the external power supply voltage VCC is applied to the chip, and generates the power-up signal PWR when reaching a predetermined potential.
    [14] Here, the power-up signal indicates that the chip is in a high-level or low-level state until the internal power-supply potential is set to a certain potential for initialization, i.e., .
    [15] However, as shown in FIG. 2, if the external power supply voltage VCC is input with ripple noise, the state of the power-up signal PWR is toggled each time the constant power supply voltage is reached and the current consumption is increased. In the worst case, A problem occurs.
    [16] In particular, when the power supply voltage is lowered, a gap between a power supply potential level at which a power-up signal is generated and an operation power supply potential level becomes small, noise is generated at the power supply potential, and an undesired power-up signal PWR is generated, Occurs.
    [17] SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-described problems by providing a time hysteresis apparatus which generates a power-up signal by maintaining a potential higher than a predetermined level for a predetermined period of time, Up detection device capable of generating a power-up detection signal.
    [1] 1 is a circuit diagram showing a conventional power-up detection apparatus;
    [2] Fig. 2 is an operational timing diagram of the power-up detecting device shown in Fig. 1. Fig.
    [3] 3 is a circuit diagram showing a power-up detection apparatus according to the present invention;
    [4] 4 is a detailed circuit diagram of the delay unit shown in Fig.
    [5] 5 is an operation timing diagram of the power-up detection apparatus according to the present invention shown in Figs. 3 and 4. Fig.
    [18] According to an aspect of the present invention, there is provided a power-
    [19] Voltage distributing means for distributing the input power supply voltage at a predetermined ratio;
    [20] Potential detecting means for comparing the potentials distributed by the voltage distributing means with specific potentials and outputting the comparison result; And
    [21] And buffer means for changing the level of the comparison result when the potential of the comparison result output from the potential sensing means is maintained for a predetermined period.
    [22] The above and other objects and features of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
    [23] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    [24] 3 is a circuit diagram showing a power-up detecting apparatus according to the present invention.
    [25] The power-up detection device includes a voltage divider 10 for distributing the power supply voltage VCC at a constant ratio, a resistor R11 having one terminal connected to the power supply voltage VCC, and a ground voltage VSS connected to the other terminal of the resistor R11, An inverter INV11 for inverting the potential N1 of the common node of the resistor R11 and the NMOS transistor NM10, and a signal N2 output from the inverter INV11 And outputs a power-up signal PWR.
    [26] Here, the voltage divider 10 includes two resistors R12 and R13 connected in series between the power supply voltage VCC and the ground voltage, and outputs the potential N0 distributed from the common node of the two resistors R12 and R13.
    [27] The filter unit 20 includes a high filter unit 21 for shifting the potential of the power-up signal PWR to a high level only when the potential N2 output from the inverter INV11 remains at a high level for a predetermined period of time, Up signal PWR to a low level only when the power-up signal PWR maintains the low level for a predetermined time.
    [28] The high filter unit 21 includes a delay unit 23 for delaying the signal N2 output from the inverter INV11 by a predetermined time, a NAND gate ND11 for negatively logically multiplying the signal N2 output from the inverter INV11 and the delay unit 23 .
    [29] The low filter unit 22 includes a delay unit 24 for delaying the signal N3 output from the high filter unit 21 by a predetermined time and a delay unit 24 for delaying the signal N3 output from the high- And a NAND gate ND12 which negatively logically multiplies the signal.
    [30] 4 is a detailed circuit diagram of the delay unit shown in FIG. Although a structure using a NAND gate is used here, a delay circuit of various structures may be used depending on the system and the application to be used.
    [31] Each of the delay units 23 and 24 includes inverters INV21 and INV22 for sequentially inverting the signal N2 output from the inverter INV11, a NAND gate ND21 for negatively multiplying the signal N2 output from the inverter INV11 and the signal output from the inverter INV22, An inverter INV23 for inverting the signal output from the gate ND21, a NAND gate ND22 for negatively logically multiplying the signal N2 output from the inverter INV11 and the signal output from the inverter INV23, And an inverter INV24 for outputting.
    [32] FIG. 5 is a timing chart showing the operation timing of the power-up detecting apparatus according to the present invention shown in FIG. 3 and FIG.
    [33] When the external power supply voltage VCC is input with ripple noise, when the constant potential is reached and the power-up signal PWR is maintained at a high level when the constant voltage is maintained for a predetermined time, that is, Transit. Therefore, even if a short pulse type noise having a high level of the power supply voltage VCC is input and a predetermined potential or more arrives, the power-up signal PWR does not transition to the high level because the high level is not maintained for a certain period of time.
    [34] Even if the power supply voltage VCC has a low level of short-pulse-like noise and falls below a predetermined potential, the power-up signal PWR does not maintain a constant potential for a certain period of time, It does not transition to the low level.
    [35] The delay time of each of the delay units 23 and 24 can be set at design time according to the size of the high level and the low level interval of the inputted noise pulse and the delay time can be adjusted by programming when the variable delay circuit is used.
    [36] As described above, the power-up detection apparatus according to the present invention generates a power-up signal only when the input external power supply voltage maintains the current state for a predetermined period or more even if the state changes due to noise. There is an effect that can be done.
    [37] It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.
    权利要求:
    Claims (11)
    [1" claim-type="Currently amended] Voltage distributing means for distributing the input power supply voltage at a predetermined ratio;
    Potential detecting means for comparing the potentials distributed by the voltage distributing means with specific potentials and outputting a comparison result; And
    And buffer means for changing the level of the comparison result when the comparison result output from the potential sensing means is maintained at a constant potential for a predetermined period of time.
    [2" claim-type="Currently amended] The method according to claim 1,
    Wherein the buffer means comprises: a first noise filter for changing a level of the comparison result when the comparison result output from the potential sensing means is maintained at a high level for a predetermined period or more; And
    And a second noise filter for changing the level of the comparison result when the state of the signal output from the first noise filter is maintained at a low level for a predetermined period or longer.
    [3" claim-type="Currently amended] 3. The method of claim 2,
    The first noise filter includes: delay means for delaying a comparison result output from the potential sensing means by a predetermined time; And
    And a calculation means for logically calculating the comparison result and the signal output from the delay means.
    [4" claim-type="Currently amended] The method of claim 3,
    Wherein the predetermined delay time of the delay means is set longer than the high level maintenance period of the noise of the external power supply voltage.
    [5" claim-type="Currently amended] 3. The method of claim 2,
    Wherein the second noise filter includes: delay means for delaying a signal output from the first noise filter by a predetermined time; And
    And a calculation means for logically calculating the comparison result and the signal output from the delay means.
    [6" claim-type="Currently amended] 6. The method of claim 5,
    Wherein the predetermined delay time of the delay means is set longer than the low level maintenance period of noise of the external power supply voltage.
    [7" claim-type="Currently amended] 7. The method according to any one of claims 3 to 6,
    Wherein the delay means includes a variable delay line capable of adjusting a delay time.
    [8" claim-type="Currently amended] The method according to claim 1,
    Wherein the buffer means comprises: first delay means for delaying a comparison result output from the potential sensing means by a predetermined time;
    A first NAND gate for negatively multiplying the comparison result and the signal output from the first delay means;
    Second delay means for delaying a signal output from the first NAND gate for a predetermined time; And
    And a second NAND gate for negatively multiplying the signal output from the first NAND gate and the signal output from the second delay unit.
    [9" claim-type="Currently amended] 9. The method of claim 8,
    Wherein the predetermined delay time of the first delay means is set to be longer than the high level of the noise of the external power supply voltage.
    [10" claim-type="Currently amended] 9. The method of claim 8,
    Wherein the predetermined delay time of the second delay means is set longer than the low level maintenance period of noise of the external power supply voltage.
    [11" claim-type="Currently amended] The method according to any one of claims 8 to 11,
    Wherein the delay means includes a variable delay line capable of adjusting a delay time.
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    同族专利:
    公开号 | 公开日
    US6873192B2|2005-03-29|
    US20040124894A1|2004-07-01|
    KR100583097B1|2006-05-23|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-12-31|Application filed by 주식회사 하이닉스반도체
    2002-12-31|Priority to KR20020088153A
    2004-07-07|Publication of KR20040061853A
    2006-05-23|Application granted
    2006-05-23|Publication of KR100583097B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR20020088153A|KR100583097B1|2002-12-31|2002-12-31|Apparatus for detecting power up|
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